Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop than acquires the phase of the input data, and ensures the phase of the output signals track changes in the phase of the output data. The loop damping of the circuit is dependent of the value of user selected capacitor, this defines jitter peaking and performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 x 105 bit periods when using damping factor of 5.