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8-bit 5.5V Quad Voltage Output D/A Converter

Model: AD5307

  • Four 8-bit DACs in 16-lead TSSOP
  • Low power, single supply operation from 2.5V to 5.5V supply
  • Consumes 1.2mW at 3V and 2.5mW at 5V
  • Rail-to-rail output with a slew rate of 0.7V/us
  • 3-wire serial interface with clock rates up to 30MHz
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The AD5307 are quad 8-bit buffered voltage-output DACs in 16-lead TSSOP that operate from single 2.5V to 5.5V supplies and consume 400uA at 3V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7V/us. The AD5307 utilize versatile 3-wire serial interfaces that operate at clock rates up to 30 MHz; these parts are compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the four DACs are derived from two reference pins (one per DAC pair). These reference inputs can be configured as buffered or unbuffered inputs. Each part incorporates a power-on reset circuit, ensuring that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears all DACs to 0V. The outputs of all DACs can be updated simultaneously using the asynchronous LDAC input. Each part contains a power-down feature that reduces the current consumption of the device to 300nA at 5V (90nA at 3V). The parts can also be used in daisy-chaining applications using the SDO pin.

  • Four 8-bit DACs in 16-lead TSSOP
  • Low power, single supply operation from 2.5V to 5.5V supply
  • Consumes 1.2mW at 3V and 2.5mW at 5V
  • Rail-to-rail output with a slew rate of 0.7V/us
  • 3-wire serial interface with clock rates up to 30MHz
  • Guaranteed monotonic by design
  • Power-on-reset to zero volts
  • Double-buffered input logic
  • Output range ofO-VREF O-2VREF
  • SPIâ„¢, QSPIâ„¢, MICROWIREâ„¢ and DSP-compatible 3-wire serial interface
  • Simultaneous update of DAC outputs via LDAC pin (active low)
  • Asynchronous clear facility via CLR pin (active low)
  • SDO daisy-chaining option
  • Buffered/unbuffered reference input options for each DAC pair
 
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