The references for the four DACs are derived from two reference pins (one per DAC pair). These reference inputs can be configured as buffered or unbuffered inputs. Each part incorporates a power-on reset circuit, ensuring that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears all DACs to 0V. The outputs of all DACs can be updated simultaneously using the asynchronous LDAC input. Each part contains a power-down feature that reduces the current consumption of the device to 300nA at 5V (90nA at 3V). The parts can also be used in daisy-chaining applications using the SDO pin.