The AD5362 offers guaranteed operation over a wide supply range with VSS from -4.5 V to -16.5 V and VDD from +8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.

The AD5362/AD5363 has a high-speed serial interface, which is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register.

Each DAC output is amplified and buffered on-chip with respect to an external SIGGND input. The DAC outputs can also be switched to SIGGND via the CLR pin.