The ADAU1978 incorporates four high performance, analog-to digital converters (ADCs) with 2Vrms capable ac-coupled inputs. The ADCs use a multibit sigma-delta architecture with continuous time front end for low EMI. An I 2 C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.